In recent years, demand for non-volatile semiconductor memory devices which are compact and have large capacity has been increasing rapidly. A NAND type flash memory device, in which higher integration and larger capacity are expected as compared with a conventional NOR type flash memory device, has attracted attention.
FIG. 1 shows an example of a relationship between threshold voltage (Vt) distributions in a multi-level NAND type flash memory device which stores 2-bit data in one memory cell by a multi-level cell (MLC) method. In this particular example, the 2- bit data stored to one memory cell are allocated as data of a different page. In other words, in a NAND type flash memory device, reading-out data and programming operation are performed on every page unit such as 2 Kbytes or 512 bytes; in the case of performing such a multi-level storing, data corresponding to two row addresses are stored to one memory cell. They are hereinafter called “upper page” and “lower page” respectively.
In the example shown in FIG. 1, initially, a status of a memory cell is an erased cell “11”. Then, data are programmed into a lower page of the memory cell. In doing so, in the case of programming “0” data into the lower page, programming is performed, shifting the threshold voltage (Vt) of the memory cell from “11” distribution to “10” distribution (refer to the upper section of FIG. 1). In addition, in the case of programming “1” data into the lower page, the threshold voltage (Vt) of the memory cell is not shifted (not shown in the figures).
Next, data is programmed into the upper page of the memory cell. In the case of programming “0” data into the upper page and storing “1” data to the lower page, programming is performed shifting the threshold voltage (Vt) of the memory cell from “11” distribution to “01” distribution (refer to the lower section of FIG. 1). Also, in the case of programming “0” data to the upper page and storing “0” data on the lower page, programming is performed shifting the threshold voltage (Vt) of the memory cell from “10” distribution to “00” distribution (refer to the lower section of FIG. 1).
In this example, reading-out data of the lower page is performed by performing A read-out after C read-out so as to output data of C read-out and A read-out (refer to upper section of FIG. 1), and reading-out of data of the upper page is performed by performing B read-out so as to output data of B read-out (refer to lower section of FIG. 1).